1. Field of the Invention
This invention generally relates to serial communication systems dependent upon extracting a clock and, more particularly, to a system and method for modifying the phase of a clock used in a Hogge phase detector.
2. Description of the Related Art
As noted in U.S. Pat. No. 6,421,404 (Nakamura), in a serial communication system such as an optical communication system, it is necessary to extract a clock component (or signal) from a serial data sequence at the receiving side, so as to receive data based on the extracted clock signal. The circuit for extracting a clock signal from a serial data sequence is called a clock-recovery circuit. This clock-recovery circuit is an application of a phase-locked loop (PLL).
FIG. 1 depicts a conventional PLL (prior art). The reference symbol PD indicates a phase-difference detector, which detects a phase difference between a clock signal output from the VCO (voltage-controlled oscillator) and an input data-signal sequence, and determines whether the current phase is advanced or delayed and outputs the determined results as phase-difference signals. The phase-difference signals, a set of pulse signals whose pulse widths are proportional to each phase difference, are output from the “reference” terminal and the “phase” terminal at the output side. In this clock-recovery circuit, these reference and phase signals are fed back (as an input signal) via a charge-pump circuit and a low-pass filter into the VCO, so that the phase of the extracted clock signal corresponds to that of the data input signal.
FIG. 2 is a depiction of a conventional Hogge phase-difference detector (prior art).
FIG. 3 is a timing chart illustrating the operation of the circuit of FIG. 2 (prior art). Considering FIGS. 2 and 3, the Hogge PD comprises a flip-flop circuit FF1 into which a signal is input at (timing corresponding to) a rising edge of the clock signal, another flip-flop circuit FF2 which operates at (timing corresponding to) a decaying (or falling) edge of the clock signal, and two exclusive OR circuits XOR1 and XOR2. The exclusive OR (XOR1) between the data input signal and the output of FF1 is calculated so as to detect a phase difference between the clock signal and the data input signal, and a pulse signal whose pulse width corresponds to the detected phase difference is output from the phase (up) terminal. On the other hand, when a pulse signal is output from the phase terminal, a pulse signal whose pulse width corresponds to half of the clock period is output from the reference (down) terminal. Further, reference pulses are generated when data changes. That is, the output of FF2 is a different state than the input of FF2.
As shown in FIG. 3, in the time from 3.0 nanoseconds (ns) to 4.0 ns, the difference between the rise timing of the clock signal and the transition timing of the data input signal becomes half of the clock period. The pulse width of the signal from the phase terminal is half of the clock period. Therefore, the circuit of FIG. 2 can detect the phase difference. The PD of FIG. 1 is able to detect such phase differences, thereby realizing a clock-recovery circuit.
The circuit in FIG. 2 also has a data-recovery function for receiving and outputting data based on the extracted clock signal. That is, both (i) detection of the phase difference between the input data sequence and the extracted clock signal and (ii) data-receiving operation can be executed. However, a clock signal whose frequency can agree with the frequency of the data input signal (i.e., the data rate) is necessary. That is, as shown in the timing chart of FIG. 3, if the transition (between the high level and the low level) of the data input signal appears with a minimum period of 0.25 ns (see the section between 3 ns to 4 ns), then the period of the clock signal must also be 0.25 ns. Here, each “transition” of the data input signal corresponds to a period from a rise to a decay (or fall) of the data input signal, or to a period from a decay to a rise of it. The period of the high level or the low level of the clock signal is 0.125 ns, that is, half of the clock period. Therefore, the clock signal must maintain a frequency two times as high as the data rate.
In optical channels that may suffer from polarization mode dispersion (PMD) or other types of amplitude or phase distorting effects, the bit error rate (BER) of the system may be improved by adjusting the sampling point of the input data. That is, the BER can potentially be improved if the clock can be “decoupled” from the input data, and the data sampled with a different phase of the clock.
It would be advantageous if the clock phase used by a Hogge PD could be modified.
It would be advantageous if the modified Hogge phase detector clock could be used to sample data.
It would be advantageous if the modified Hogge phase detector clock could be used to sample data suffering from PMD, or other distorting effects, to improve the BER of received data.